Interface Technology SR5030 Variable Voltage I/O Module
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Interface Technology SR5030 Variable Voltage I/O Module

Features

  • 16 Input and 16 Output Pins per Module
  • 4 Programmable Input and Output Levels
  • 64K Vectors per Channel
  • 50 MHz Data Rate

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This Interface Technology SR5030 Variable Voltage I/O Module is used, and in good condition.



Stock # 52427-1




This Interface Technology SR5030 Variable Voltage I/O Module is used, and in good condition.

Lead Time: 14-21 Business Days



Stock # 52427-10




This Interface Technology SR5030 Variable Voltage I/O Module is new from surplus stock. Cable Assembly, P/N: 20011538-003, included.



Stock # 52427-2




This Interface Technology SR5030A Variable Voltage I/O Module is used and in excellent condition.



Stock # 52427-3



  • Description
  • Tech Specs
  • Datasheets / Manuals 
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Description

The SR5030 provides a variable voltage interface to the unit under test (UUT). Up to 20 SR5030 I/O modules can be controlled by the SR5010 Timing/Control Module for a total of 320 I/O pins. The inputs and outputs of the SR5030 can operate over a range of -6 volts to +15 volts. This range is sufficient to cover TTL, CMOS, ECL, and most military and non-standard logic levels. The SR5030 Variable Voltage I/O Module contains 16 stimulus and 16 response channels on a single VXI C-size card.

Seven Distinct I/O Memory Types
The SR5030 I/O Module contains seven separate memory banks, each 64K vectors in depth, for generating stimulus patterns, expected response patterns, and recording UUT response data. All memory banks operate at full 50 MHz data rates.

Stimulus Memories contains the Output, Algorithmic and Tristate patterns, which are used to define the stimulus output to the UUT. The Response Memories contains the Expect, Algorithmic, and Mask patterns, which are used to define the expected response from the UUT.

Record Memory is used to store either the UUT response data or the result of the comparison between the UUT response data and the Expect pattern. It is operated independently in a manner much like a logic analyzer. A sixteen-level state machine and nine system-wide digital comparators are used to control what data is saved in the memory. In addition to the record memory, each input channel is provided with a 16-bit CCITT CRC register for Signature Analysis applications.

Timing and Voltage Control
Each I/O module contains 10 separate timing generators for stimulus and response edge placement. Output pins can select from 4 timing generators to define the leading and trailing edges of each stimulus pin. Groups of eight output pins share an independent set of 4 timing generators for a total of 8 stimulus timing generators per card. Response pins can select from 2 response timing generators to define the sample and compare edges, or the 2 response timing generators can be combined together for window compare with glitch detection.

The output high and low voltages and the input logic threshold voltage are independently user programmable in groups of four channels. The output skew rate is internally controlled according to the output level.

Multiple Data Formats
Stimulus pins may be independently programmed for any of the following formats: Non Return to Zero (NRZ), Return to Zero (RZ), Return to One (RONE), Return to Complement (RTC) and Return to Inhibit (RI).
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Specifications