Abaco Systems / VMIC VMIPCI-5579-500 13.4 Mbyte/s Fiber-Optic Reflective Memory with Interrupts

The GE Fanuc / VMIC VMIPCI-5579 13.4 Mbyte/s Fiber-Optic Reflective Memory with Interrupts is a member of a high-performance, daisy-chained, fiber-optic network. Data is transferred by writing to on-board global RAM. The data is automatically sent to the location in memory on all Reflective Memory boards on the network.

The Reflective Memory concept provides a very fast and efficient way of sharing data across distributed computer systems. The GE Fanuc / VMIC VMIPCI-5579 Reflective Memory interface allows data to be shared between up to 256 independent systems (nodes) at rates up to 13.4 Mbyte/s. Each Reflective Memory board may be configured with 32 or 64 Mbyte of on-board RAM. The local RAM provides fast read access times to stored data. Writes are stored in local RAM and broadcast over a high-speed fiber-optic data path to other Reflective Memory nodes. The transfer of data between nodes is software transparent, so no I/O overhead is required. Transmit and Receive FIFOs buffer data during peak data rates to optimize CPU and bus performance to maintain high data throughput.

The Reflective Memory also allows interrupts to one or more nodes by writing to a byte register. Three separate, user-definable interrupts may be used to synchronize a system process, or used to follow any data. The interrupt always follows the data to ensure the reception of the data before the interrupt is acknowledged.

The VMIPCI-5579 requires no initialization unless interrupts are being used or endian byte swapping is desired.

Each node on the system has a unique identification number between 0 and 255. The node number is established during hardware system integration by placement of jumpers on the board. This node number can be read by software by accessing an on-board register. In some applications, this node number would be useful in establishing the function of the node.

LINK ARBITRATION

The VMIPCI-5579 system is a fiber-optic daisy chain ring. Each transfer is passed from node-to-node until it has gone all the way around the ring and reaches the originating node. Each node retransmits all transfers that it receives except those that it originated. Nodes are allowed to insert transfers between transfers passing through.

INTERRUPT TRANSFERS

In addition to transferring data between nodes, the VMIPCI-5579 will allow any processor in any node to generate an interrupt on any other node. These interrupts would generally be used to indicate to the receiving node that new data has been sent and is ready for processing. These interrupts are also used to indicate that processing of old data is completed and the receiving node is ready for new data.

Three interrupts are available. The user may define the function for each interrupt. Any processor can generate an interrupt on any other node on the network. In addition, any processor on the network can generate an interrupt on all nodes on the network. Interrupts are generated by simply writing to a VMIPCI-5579 register.

All data and interrupt command transfers contain the node number of the node that originated the transfer. This information is used primarily so the originating node can remove the transfer from the network after the transfer has traversed the ring. The node identification is also used by nodes receiving interrupt commands. When a node receives an interrupt command for itself, it places the identification number of the originating node in a FIFO. Up to 63 interrupts can be stacked in the FIFO. During the interrupt service routine, the identification of the interrupting node can be read from the FIFO. Sixteen bits of data are also transmitted with the interrupt and stored in the interrupt FIFO.

PCI INITIATOR/DMA CAPABILITIES

The VMIPCI-5579 supports DMA operations. The DMA capability is initiated by a PCI host. After the DMA engine is initialized by a host, the VMIPCI-5579 will request the PCI bus as appropriate and move up to 64 Mbyte as a PCI initiator. This capability removes the CPU from the responsibility of requesting the PCI bus and moving the data itself. This feature is very useful for moving large blocks of data. The PCI architecture ensures the VMIPCI-5579 does not monopolize the PCI bus during this process. Large DMA blocks will automatically be split into smaller bursts on the PCI bus by the DMA engine. The VMIPCI-5579 can be programmed to issue a PCI interrupt at the conclusion of a DMA transfer or the host can poll the status of the DMA process. The status of the DMA can be accessed from the board, if required. Although the DMA engine can do both DMA reads and DMA writes, they cannot occur simultaneously. The VMIPCI-5579 can burst data onto the PCI bus at a maximum rate of 132 Mbyte/s and sustain 22 Mbyte/s. If the target operates at a slower rate, the PCI handshaking capabilities will throttle the data rate.

ERROR MANAGEMENT

Errors are detected by the VMIPCI-5579 with the use of the error detection facilities of the Hot Link chipset and additional parity encoding and checking. The error rate of the VMIPCI-5579 is a function of the rate of errors produced in the optical portion of the system. This optical error rate depends on the length and type of fiber-optic cable. Assuming an optical error rate of 10^-12, the error rate of the VMIPCI-5579 is 1.6 x 10^-10 transfers/transfer.

However, the rate of undetectable errors is less than 2.56 x 10^-20 transfers/transfer. When a node detects an error, the erroneous transfer is removed from the system and a PCI bus interrupt is generated, if enabled.

The VMIPCI-5579 can be operated in a redundant transfer mode in which each transfer is transmitted twice. In this mode of operation, the first of the two transfers is used unless an error is detected in which case the second transfer is used. In the event that an error is detected in both transfers, the node removes the transfer from the system. The probability of both transfers containing an error is 2.56 x 10^-20, or about one error every 1,470,000 years at maximum data rate.

ENDIAN CONVERSIONS

Data lane steering can be configured in a Control Register to allow CPUs of different architectures to communicate. Byte swap, Word swap, and Byte-Word swap options are available.

PROTECTION AGAINST LOST DATA

Data received by the node from the fiber-optic cable is error checked and placed in a receive FIFO. Arbitration with accesses from the PCI bus then takes place, and the data is written to the node's RAM and to the node's transmit FIFO. Data written to the board from the PCI bus is placed directly into RAM and into the transmit FIFO. Data in the transmit FIFO is transmitted by the node over the fiber-optic cable to the next node.

The product is designed to prevent either FIFO from becoming full and overflowing. It is important to note the only way that data can start to accumulate in FIFOs is for data to enter the node at a rate greater than 13.4 Mbyte/s or 6.7 Mbyte/s in redundant mode. Since, data can enter from the fiber and from the PCI bus, it is possible to exceed these rates. If the transmit FIFO becomes half-full, a bit in the Status Register is set. This is an indication to the node's software that subsequent writes to the Reflective Memory should be suspended until the FIFO is less than half-full. If the half-full indication is ignored and the transmit FIFO becomes full, then writes to the Reflective Memory will be acknowledged with a STOP*. No data will be lost.

NETWORK MONITOR

There is a bit in a Status Register that can be used to verify that data is traversing the ring (that is, the ring is not broken). This can also be used to measure network latency. VMIC offers single fiber cable assemblies and adapters that are compatible with the VMIPCI-5579 in length ranging from 1.5 to 1,000 m. These cable assemblies are U.L./NEC-rated OFNP and have a 2.5 mm SC-style connector on each end.

Product Family: VMIPCI-5579, VMIPCI 5579, VMIPCI5579