Acromag IP-EP200 JTAG-Reconfigurable Cyclone II FPGA Digital I/O Modules
  • acromag_ip_ep201_view1_201591122119
  • acromag_ip_ep201_view2_201591122119

Acromag IP-EP200 JTAG-Reconfigurable Cyclone II FPGA Digital I/O Modules

Features

  • Altera Cyclone II EP2C20 FPGA
  • FPGA Programmable via JTAG Port or IP Bus
  • LVTTL External Clock Connected Directly to the FPGA
  • Programmable PLL-Based Clock Synthesizer

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  • Description
  • Tech Specs
  • Datasheets / Manuals 
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Description

The IP-EP200 JTAG-Reconfigurable Cyclone II FPGA Digital I/O Modules provide a user-customizable Altera Cyclone II FPGA on an Industry Pack (IP) module. The module allows users to develop and store their own instruction set in the FPGA for adaptive computing applications. Typical uses include specialized communication systems over RS422/485 networks, test fixture simulation of signals over TTL-switched lines, and analysis of acquired data using specialized mathematical formulas such as those developed with MathWorks’s MatLab software

The FPGA on Acromag’s IP-EP200 modules can control up to 48 TTL or 24 RS485 I/O signals or a mix of both types. Another model interfaces 24 LVDS I/O channels. User application programs are downloaded through the JTAG port or via the IP bus directly into the FPGA. A pre-programmed internal CPLD facilitates initialization by acting as the bus controller during power-up and while the program is downloading. This bus controller is limited to functions necessary for power-up and down-loading. After the program downloads, the FPGA takes control of the IP bus and the CPLD disables.

Product Family: IP-EP200
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Specifications

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Resources

Manuals, Datasheets, Drivers, Links

Acromag IP-EP201Datasheet (pdf) 
Link to Acromag Website