PUP55-23-M5 Intel VisionICE / VisionICE II Power Supply

The Intel / Wind River / EST VisionICE Scalable Emulators for PowerPC are designed for full life-cycle development, including chip and system evaluation, software simulation, hardware prototyping, hardware/software integration, source-level debugging, performance tuning, and production test.

EST's VisionICE emulator for PowerPC is comprised of the following components:

VisionCONTROL, the base system and target controller for the VisionICE emulator. It utilizes on-chip debugging services which are embedded in the MPC8xx cores. These debugging services operate in a similar fashion to the Background Debug Mode of Motorola's 683xx family. On its own, VisionCONTROL offers entry-level system debugging which can be upgraded later to a full visionICE system.

VisionNET for full Ethernet network support. This high performance option allows shared and remote debugging from anywhere on a LAN. It also significantly reduces the amount of time it takes to download large software images to the target PowerPC.

VisionEVENT, which may be added to VisionICE when high-end, real-time emulation and logic analysis is required during debugging. VisionEVENT provides state-of-the-art event isolation with 64 132-bit hardware breakpoints which may be used to break the processor, or to trigger a fully selectable 128 Kbytes by 96-bit real-time trace buffer. VisionEVENT also includes a 48-bit time stamp for precise performance tuning.