V520-ZB11 DynamicSignals Time Code Interface VXIbus Module

The DynamicSignals / Kinetic Systems V520 Series Time Code Interface VXIbus Modules are a single-width, C-sized VXIbus module that provides time stamp information for VXIbus-based data acquisition systems. In data acquisition, it is often important to provide time information for each block of data acquired. Reading the V520 allows the time stamp to be included in the acquired data block. Versions of the module are manufactured for use either alone or in conjunction with a Datum Model 9300A Time Code Generator/Translator.

The Datum Generator/Translator or an internal crystal-controlled counter chain provides timing information to the V520 with a 44-bit parallel BCD representation for days, hours, seconds, and milliseconds. The time code has a resolution of one millisecond. The Datum unit can use an IRIG-B time code or an internal clock as the original source. The internal oscillator on the V520 provides an accuracy of +/-0.01%.

Time code information is "frozen" in a V520 register either by software command or by a front-panel TTL-level pulse.

Once the time information has been latched, it will remain so until the module receives another software or external trigger (i.e., subsequent read operations will yield the same data). Special buffering is incorporated to preclude any metastable effects caused by changing data in the time source during acquisition. A watchdog timer is included to monitor the one millisecond strobe from the time source. If a subsequent strobe does not occur within 1.5 milliseconds, then the 44-bit time pattern is set to an "all 1's" error state until the proper strobe rate returns. If a latch command or external strobe is received while the module is in an error condition, the "all 1's" pattern will be latched in the data registers. The current state of the error condition can be tested with a software command.

The V520 also contains a 16-word, 16-bit scratchpad memory. This general purpose RAM can be written or read. One application of this memory in a data acquisition system is to provide a set of unique (or nearly unique) words to form a sync header. The memory can be written during set-up and the appropriate number of words read as a part of each acquisition block.

The V520 supports both static and dynamic configuration capabilities. Access to the data is through memory locations indicated by the Offset Register within the VXIbus Configuration Register set, using A24/16, D16 data transfers.