SR5040S Interface Technology Differential ECL I/O Module

The SR5040 ECL I/O Module provides 32 stimulus pins and 32 response pins in a single C-size VXI slot. Up to 20 I/O modules may be controlled by the SR5010 Timing/Control Module for a total of 640 I/O pins. Intermodule communication occurs through a VXI register-based interface and VXI direct memory access.

The SR5040 I/O Module contains six separate memory banks, each 64K vectors in depth, for generating stimulus patterns, expected response patterns, and recording UUT response data. All memory banks operate at full 50 MHz data rates.

Stimulus Memories contain the Output and Algorithmic patterns, which are used to define the stimulus output to the UUT. The Response Memories contains the Expect, Algorithmic, and Mask patterns, which are used to define the expected response from the UUT. The Mask Memory provides a means to ignore individual response data bits on a vector by vector basis. Algorithmic Memory is used to define the arithmetic operations needed to generate stimulus and response data with the algorithmic hardware.

Record Memory is used to store either the UUT response data or the result of the comparison between the UUT response data and the Expect Memory. It is operated independently in a manner much like a logic analyzer. A sixteen-level state machine and nine system-wide digital comparators are used to control what data is saved in the memory. In addition to the record memory, each input channel is provided with a 16-bit CCITT CRC register for Signature Analysis applications.

Each I/O module contains 18 separate timing generators for stimulus and response edge placement. Each output pin can select from 4 timing generators to define the leading and trailing edges of each stimulus pin. Each group of eight output pins share an independent set of 4 timing generators for a total of 16 stimulus timing generators per card. Each response pin can select from 2 response timing generators to define the sample and compare edges, or the 2 response timing generators can be combined together for window compare with glitch detection.