Product Family: 5998-01-458-4968, 5998014584968
- 32 Input and 32 Output Pins per Module
- 64K Vectors per Channel
- RAM-Backed and Algorithmic Pattern Generation
- NRZ, RZ, RONE, RTC, and RI Output Data Formats Supported
The SR5020 I/O Module contains seven separate memory banks, each 64K vectors in depth, for generating stimulus patterns, expected response patterns, and recording UUT response data. All memory banks operate at full 50 MHz data rates.
Stimulus Memories contains the Output, Algorithmic and Tristate patterns, which are used to define the stimulus output to the UUT. The Response Memories contains the Expect, Algorithmic, and Mask patterns, which are used to define the expected response from the UUT.
Record Memory is used to store either the UUT response data or the result of the comparison between the UUT response data and the Expect pattern. It is operated independently in a manner much like a logic analyzer. A sixteen-level state machine and nine system-wide digital comparators are used to control what data is saved in the memory. In addition to the record memory, each input channel is provided with a 16-bit CCITT CRC register for Signature Analysis applications.
Interface Technology SR5020 TTL I/O Module Manuals, Datasheets, Drivers, Links
Interface Technology SR5020 TTL I/O Module Specs
| General | |
| Manufacturers | Interface Technology |
| Model | SR5020 |
| Condition | Used and in Excellent Condition |
| NSN | 5998-01-458-4968, 5998014584968 |
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