SR5020A Interface Technology TTL I/O Module

The SR5020 module has a dual processor architecture that is optimized for digital testing. The System Processor, the powerful 68030 running at 25 MHz, provides the VXI Bus message-based interface to the Slot-0 Controller. The Control Processor is the real-time digital test engine controlling the conditional test branching, looping, sequencing and logic analysis trigger evaluation.

The SR5020 I/O Module contains seven separate memory banks, each 64K vectors in depth, for generating stimulus patterns, expected response patterns, and recording UUT response data. All memory banks operate at full 50 MHz data rates.

Stimulus Memories contains the Output, Algorithmic and Tristate patterns, which are used to define the stimulus output to the UUT. The Response Memories contains the Expect, Algorithmic, and Mask patterns, which are used to define the expected response from the UUT.

Record Memory is used to store either the UUT response data or the result of the comparison between the UUT response data and the Expect pattern. It is operated independently in a manner much like a logic analyzer. A sixteen-level state machine and nine system-wide digital comparators are used to control what data is saved in the memory. In addition to the record memory, each input channel is provided with a 16-bit CCITT CRC register for Signature Analysis applications.