Full Rio Ellips High Performance Frame Grabber PCI Card

The Ellips Rio High Performance Frame Grabber PCI Card is designed to get the most out of any SVideo/composite color or standard black and white camera, the Ellips Rio is a high performance PCI frame grabber, targeted at real-time industrial image processing applications. The Rio is made in two versions: basic version with one input module, and full version with two input modules.

Some grabbers based on a PCI SVGA controller have an image port that allows write access to the video memory from an external access bus (typical bandwidth 45 MB/s). Although this method offers live video on the desktop without hogging the PCI bus, reading the image back from video memory to main memory suffers from slow memory access due to the nature of these SVGA controllers: typical write bandwidth from PCI to SVGA is up to 90 MB/s, whereas read bandwidth from SVGA to PCI is limited to approximately 7 MB/s. Therefore SVGA-controllers based PCI grabbers are generally not suited for real-time imaging applications.

Some PCI grabbers employ efficient PCI burst transfers, but lack flexible transfer controller capabilities. Therefore, more data is sent over the PCI bus than is actually needed, thus slowing the system down. For example, when tracking moving objects, the region of interest changes for every video frame. This calls for changing the region of interest at field rate.

The Ellips Rio offers PCI bus master DMA, allowing burst transfers of up to 132 MB/s (depending on the quality of the main board) without tying up the main CPU, combined with a very flexible transfer controller. Using a Register Program Sequencer, input window, output destination, scaling, and clipping can be reprogrammed on a line-by-line basis without CPU intervention. The sequencer program can be changed every field to incorporate complex changes of the image parts transferred over the PCI bus to main memory, thus tracking moving objects.

The PCI interface supports virtual memory addressing for operating systems running virtual demand paging (like Windows). The integrated Memory Management Unit (MMU) translates linear to physical addresses using a page table in system memory provided by the software driver. The MMU supports op to 4 MB of virtual address space per DMA channel.