EVE HAPS-62 High Performance ASIC Prototyping System

Achieving clock frequencies of up to 200MHz, the HAPS-60 series supports applications requiring real-time interfaces such as video, cellular data or live network traffic. The HAPS-60 series, which runs up to 30 percent faster than previous generations of HAPS products, incorporates performance enhancing technologies that are not available on other solutions. This technology advantage enables full system integration and testing of all hardware and software in a real-world environment. Software developers benefit by being able to write, execute and debug code in a near real-time system level environment, enabling the early identification and elimination of hardware and software bugs months ahead of silicon availability.

The flexible architecture of HAPS systems, combined with advanced high-capacity partitioning software and new automated high-speed Time Division Multiplexing (HSTDM), allow the HAPS60 series to achieve greater capacities than other prototyping systems. This capacity advantage allows design teams to build prototypes of very large systems on chips (SoCs). A single HAPS board can support designs up to 18M ASIC gates (more than double the capacity of the previous generation), and multiple boards can be connected together for higher capacity.

With many of the DesignWare® IP cores such as SuperSpeed USB 3.0, PCI Express® and HDMI pre-tested on HAPS systems, designers benefit from having a proven solution for system-level hardware and software prototyping using the same SoC production RTL. Using the same RTL from prototype to production reduces project schedule and risk. With pre-tested DesignWare IP, project leaders using HAPS systems can focus their engineering resources on product differentiation and system validation instead of verifying the IP portions of their prototype.

The HAPS-60 series provides advanced verification functionality, previously unavailable in prototyping systems, enabling engineers to reduce verification time by using the HAPS-60 series hardware earlier in the design cycle. Built on Synopsys' high-performance Universal MultiResource Bus (UMRBus) technology, new modes of verification include co-simulation through standard PLI and SCE-MI 2.0 transaction interfaces with Synopsys VCS and Innovator products, C/C++ programs, and other event driven simulators.