2209 Technobox 2-Channel, 16-Bit, 192 kSa/s Delta Sigma Analog-to-Digital Converter PMC Module

The Technobox 2209 2-channel, 16-Bit Analog-to-Digital converter board features two independent Delta-Sigma A:D converter channels.

Differential inputs are accommodated by two “SMB” style RF connectors for each channel. When operating in differential mode, each SMB (i.e., SMB+ and SMB-) is connected to one leg of a differential pair.

For applications requiring analog difference between two independent single-ended analog sources, connect the +SMB to one signal source, and the -SMB to the other signal source of a given channel.

Each channel may also operate with single-ended analog data. To accomplish this, leave one SMB connector of the channel unconnected.

The input signal for each channel is conditioned with a passive attenuation pad. A 1-pole R/C low pass filter provides anti-aliasing for each 64x over-sampling A:D converter channel.

A programmable gain instrumentation amplifier buffers the input signal, which is then presented to the A:D converter. Gain steps are set to 1x, 2x, 4x, and 8x for the standard product. The gain step for each channel is programmed from the host processor via the PCI bus.

Overall gain and offset for each channel is trimmed by variable resistors accessible from the PMC front panel.

The attenuation together with the programmable gain offers virtually any input signal range to be accommodated by this board. Each channel may be assembled with different attenuation and gain components.

A programmable clock generator establishes the sampling rate for each channel and is programmed over the PCI bus from the host processor. Sample rates from 7 Ks/s to 192 Ks/s are possible with the A:D converters used in this design.

Each channel has a 32K-word deep FIFO which stores the incoming 16-bit digitized data. Each FIFO is memory mapped to different addresses in the host-processor address space, as set up by the programmable base/size registers in the PCI configuration space. The 32K-word FIFO provides approximately 150 milli-seconds of program service elasticity when operating at the highest sample rate (192 Ks/s per channel).

The FIFO data are read directly by the host processor and stored in host processor’s memory for further processing. The sustained transfer rate for moving data from the FIFOS to memory is approximately 2.5 MW/s (16 bit words), which is six times the total sample rate between the two channels.

A programmable “watermark” is provided for each FIFO. When the data in the FIFO exceeds the programmed watermark, the host program is notified by a PCI interrupt. Also, the current word count for each channel may be read by the host program for polling-style software architectures.