7131 Pentek 16-Channel Multiband Receiver with A/Ds and FPGA - PMC

The Pentek Model 7131 is a general-purpose 16-channel multiband digital receiver PMC module which attaches directly to PMCcompatible baseboards. It includes both a Virtex-II FPGA and two 14-bit A/Ds for signal processing.

The Model 7131 accepts two analog RF inputs at +4 dBm full scale into 50 ohms on front panel SMA connectors. The two inputs are transformer coupled and digitized by AD6645 14-bit A/D converters. The AD6645 operates at a maximum sampling rate of 80 MHz in the standard unit and up to 105 MHz for option -100. The sampling clock can be driven from an internal 80 MHz or 100 MHz crystal oscillator, or from an external sample clock supplied through a front panel SMA connector or the front panel sync bus.

The 7131 includes four TI/Graychip GC4016 quad multiband digital downconverter chips. The maximum input sampling rate for the GC4016 is 100 MHz. Each device includes four independently tunable channels capable of center frequency tuning from DC to ƒ_S/2, where ƒ_S is the sample clock frequency. Each GC4016 accepts two 14-bit parallel inputs from the two A/D converters. A crossbar switch in each GC4016 allows all 16 channels on the board to select either of the two A/D inputs for flexible switching.

With a 100 MHz sample clock, the useable output bandwidth of each of the downconverter channels is 2.5 MHz. However, since the Model 7131 delivers parallel digital outputs from the GC4016 into the FPGA, users can take advantage of the GC4016 channel combining mode to join two or four channels into a single channel with a resulting bandwidth of 5 or 10 MHz, respectively. This supports many of the new wideband wireless standards. Since both A/D converters connect directly to the FPGAs, signals with even wider bandwidths can be accommodated.

The downconverter outputs are delivered to a Xilinx Virtex-II XC2V1000 FPGA (XC2V3000 with option -300) which is factory configured to perform various modes of data packing, formatting and channel selection. Dual port memories in the FPGA provide efficient PCI Bus transfers by buffering receiver and A/D data. The A/D outputs are also connected directly to the FPGA so that wideband A/D data can be delivered directly to the baseboard bypassing the downconverters. An A/D decimation mode allows one of every N samples to be written into the FPGA memory, where N is any integer between 1 and 4096. This overcomes the lower frequency limit on the A/D sample clock. Option -104 installs the P4 PMC connector with 37 or 64 signal line connections to the XC2V1000 or XC2V3000 FPGA respectively, for custom I/O through P4.