CPCI6115TM Motorola Transition Module

The Emerson / Motorola CPCI-6115 CompactPCI Single Board Computer is a peripheral slot CompactPCI CPU board based on the MPC7457 processor family and MV64360 PCI-Host bridge/system memory controller and the Intel 21555 PCI-to- PCI bridge. The CPCI-6115 supports up to 1.5 GB of DDR SDRAM, two PMC sites, 8MB of boot flash, 32MB of soldered flash, three Gigabit Ethernet ports and one IDE port. The CPCI-6115 also supports the CompactPCI Packet Switching Backplane (PICMG 2.16) specification. The CPCI-6115 has two planar PCI busses (PCI_0 and PCI_1). The CPCI-6115 has two planar PCI busses, both of which are controlled by the MV64360 System Controller. The MV64360 Device Controller can support up to 5 banks of devices. On the CPCI-6115, it supports the onboard flash, NVRAM/RTC, UART and programming registers. Each bank supports up to 512 MB of address space.

The Emerson / Motorola cPCI-6115 CompactPCI Single Board Computer interfaces to the CompactPCI bus via the J1 and J2 connectors as specified in the PICMG 2.0 specification. It draws +3.3 V and +5 V power, and optionally ±12 V power, from the CompactPCI backplane through these two connectors. All other required voltages are regulated onboard from the +3.3 V or +5 V power. Front panel connectors on the CPCI-6115 board include: one RJ-45 connector for the Gigabit Ethernet; one RJ-45 connector for the asynchronous serial port; a combined reset and abort switch; and two status LEDs. One additional asynchronous serial port is provided and routed to the J5 connector for rear I/O access. Two Gigabit Ethernet ports are routed to the J3 connector for PICMG 2.16 connectivity or other rear I/O access. The CPCI-6115 contains two IEEE1386.1 PCI Mezzanine Card (PMC) slots. PMC 2 is a 32/64- bit capable and supports both front and rear I/O. PMC 1 is 32-bit capable and supports both front and rear I/O. All I/O pins of PMC 2 are routed to the J5 connector. All I/O pins of PMC 1 are routed to the J3 connector.