Vertical Interconnect FermiLab VME Module

The Integrated Engineering / Fermilab Vertical Interconnect VME Module allows a standard VMEbus crate to be expanded by accessing other remote VMEbus crates over a 60 MHz serial link. The Vertical Interconnect consists of a master card and one to four slave cards. The master's memory map is segmented into 16 Mbytes blocks that are assigned to each of the four slave crates, so that a simple move instruction causes a read or write to occur on the backplane of the appropriate slave crate.

The Vertical Interconnect uses AMD's Taxi chip set to communicate at 60 MHz. A Vertical interconnect module can serve as either a master or slave module, determined by the jumpers and PLD's (programmable logic device) on the module. All slave accesses are transparent to the master crate. The slave reads and writes data, returning DTACK to the master crate, as if the VMEbus cycle was done on the master's backplane. The Vertical Interconnect allows byte, word or long word, supervisory or non-privileged memory cycles.

The Vertical Interconnect also allows the slave and master to cause an interrupt in each other's crate. The interrupt cycle returns the vector supplied by the host crate. The Vertical Interconnect also allows the master crate to cause a reset in the slave crate.