GSI GS8644Z72C-166 72Mbit Pipelined and Flow Through Synchronous NBT SRAM

The GSI GS8644Zxx Series 72Mbit Pipelined and Flow Through Synchronous NBT SRAM allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles just like GSI's ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read / single late write SRAMs.

Because it is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.

The GS8644Z18/36/72 may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edgetriggered registers that capture input signals, the device incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.