MPMC860-001 Emerson PMC Communication Controller

The Emerson / Motorola MPMC860 Series PMC Communication Controllers employ the MPC860MH PowerPC Quad Integrated Communications Controller (PowerQUICC), a versatile one-chip dual-processor architecture which provides both a high-performance general-purpose processor for application programming as well as a special-purpose communications processor module (CPM) uniquely designed for communications needs. The CPM contains features that allow the MPC860 to excel in communications and networking products as did the MC68360 QUICC which preceded it. The CPU on the MPC860 is a 32-bit PowerPC implementation that incorporates memory management units (MMUs) and instruction and data caches. The CPM provides the communication features of the MPC860. Included are a RISC processor, four serial communication controllers (SCC), two serial management controllers (SMC), one serial peripheral interface (SPI), one I2C interface, 5 Kbytes of dual-port RAM, an interrupt controller, a time-slot assigner, three parallel ports, a parallel interface port, four independent baud rate generators, and sixteen serial DMA channels to support the SCCs, SMCs, SPI, and I2C. The SDMAs provide two channels of general-purpose DMA capability for each communications channel. They offer high-speed transfers, 32-bit data movement, buffer chaining, and independent request and acknowledge logic. The addition of a multiply-and-accumulate (MAC) function on the CPM further enhances the MPC860, enabling various modem and DSP applications.

The MPMC860SC variant supports a second processor, the MC68360. This processor runs in slave mode, thus enabling the MPC860MH to use its internal CPM. The MC68360 is only present on the MPMC860SC variant where it provides two additional TDM interfaces to the SC4000 or to the framers for channel processing. The SC4000 is used as the TDM switch on the MPMC860SC. The SCbus side of the SC4000 is connected through the Pn4 connector to the carrier board. The SC4000 is capable of acting as a clock master or slave on the SCbus. The SC4000 is capable of receiving data from the processors and the two E1/T1 ports. The SCbus Message Channel output of the SC4000 is connected to the MPC860MH (SCC4) for common channel signaling. The Tundra QSpanTM PCI bridge CA91C860 provides the bridge function between the MPC860 bus and the PCI bus. It provides 32-bit addressing and 32-bit data. The QSpan supports PowerQUICC processor external bus frequencies up to 25 MHz and PCI frequencies up to 33 MHz. The interface is PCI revision 2.1 compliant.

The MPMC860 is populated with 16MB of 32-bit, 60 ns DRAM. The DRAM memory is controlled by the MPC860MH processor. The MPMC860 contains one bank of Flash memory which is populated with one 2MB device (AM29F016). The data bus of the Flash is 8-bits wide. The PMC860 is delivered with the Flash memory containing the Board Initialization and Self-Test firmware.The Dallas Semiconductor DS2154 is used as the E1 controller and the DS2152 as theT1 controller. The controller chips are capable of driving 100 Ohm E1 lines or 120 Ohm T1 lines respectively.