SR5050 Interface Technology CMOS I/O Module for SR5000

The SR5050 CMOS I/O Module provides 32 stimulus pins and 32 response pins in a single C-size slot. Up to 20 I/O modules may be controlled by the SR5010 Timing/Control Module for a total of 640 I/O pins. Input and output pins are grouped on separate connectors, providing the most efficient method of interfacing to the UUT. Bidirectional capability is accomplished by externally connecting the input pins to the output pins.

The SR5050 I/O Module contains seven separate memory banks, each 64K vectors in depth, for generating stimulus patterns, expected response patterns, and recording UUT response data. All memory banks operate at full 50 MHz data rates. The Stimulus Memories consist of the Output, Tristate and Algorithmic Output memories. The Output Memory contains the actual data patterns to be generated to the UUT. Tristate Memory provides tristate control which supports bidirectional I/O. The Algorithmic Output Memory determines which algorithmic pattern will be output. The Response Memories consist of the Expect, Mask, and Algorithmic Expect memories. The Expect Memory contains the expected response data for the UUT and is the basis for input compare operations. The Mask Memory determines which patterns are to be ignored for input response comparison. Algorithmic Expect Memory determines which algorithmic expect pattern will be compared against the UUT input response. Record Memory is used to store either the UUT response data or the result of the comparison between the UUT response data and the expected response pattern.

Stimulus pins may be independently programmed for any of the following data formats: Non-Return to Zero (NRZ), Return to Zero (RZ), Return to One (R1), Return to Complement (RC), and Return to Inhibit/Tristate (RI). Each SR5050 CMOS I/O Module contains 16 timing generators for stimulus edge placement and pulse width timing. Output pins can select from 2 pairs of timing generators to define the leading and trailing edges of each signal pin. Groups of eight output pins share an independent set of 2 timing generator pairs for a total of 8 stimulus timing generator sets per card. 100 ps edge placement resolution provides precise UUT timing for bus emulation testing, memory testing, and functional testing. Response pins can select from 2 response timing generators to define the sample and compare edges, or the 2 response timing generators can be combined together for window compare with glitch detection.