SR5260 Interface Technology 200Mhz LVDS I/O Module for SR5000

The SR5260 LVDS I/O Module provides 8 stimulus pins, 8 tristate output pins, and 8 response pins, operating at 200 MHz, in a single C-size slot. Up to 20 I/ O modules may be controlled by the SR5010A Timing/Control Module for a total of 160 I/O pins at data rates to 200 MHz.

The SR5260 I/O Module contains five separate memory banks, each 256K vectors in depth, for generating stimulus patterns, expected response patterns, and recording UUT response data. All memory banks operate at full 200 MHz data rates when configured for 8 channel operation. The Stimulus Memories contain the Output and Tristate Control patterns, which are used to define the stimulus output to the UUT. The tristate memory drives separate output pins that are used to control external pin drivers, as the SR5260’s outputs are not directly tristated. The Response Memories contain the Expect, Mask and Record memories. The Expect and Mask patterns are used to define the expected response from the UUT, and to ignore response data bits on a vector-by-vector basis. The Record Memory is used to store either the response data or the result of the comparison between the response data and the Expect Memory. It is operated independently in a manner much like a logic analyzer. A sixteen level state machine and nine system-wide comparators are used to control what data is saved in the memory. In addition to the record memory, each input channel is provided with a 16-bit CCITT CRC register for signature analysis applications.

Each I/O module contains 12 separate timing generators, eight for stimulus edge placement and four for response edge placement. The output pins use four of the stimulus timing generators to define the leading (assert) and trailing (deny) edges of the stimulus signal. Used with data formatting, the output pins acquire the ability to produce clocks and strobes within one test cycle. The response pins use the four response timing generators to define the sample and compare edges to determine when to compare and record UUT response data.

The stimulus pins may be independently programmed for any of the following formats: Non-Return-to-Zero (NRZ), Return-to-Zero (RZ), Return-to-One (RONE), Return-to-Complement (RC), and Return-to-Inhibit (RI). The formats are applied to the selected stimulus pins to force the outputs to the defined state when the pin is not actively driving the programmed state. This allows clocks and strobes of either polarity to be generated in a single test cycle, or allows bi-directional control of data busses.