DC-1 Access Dynamics I/O Controller

The Access Dynamics DC-1 I/O Controller is a high performance and versatile I/O controller which transfers data with complete independence from the VME bus using the VME Subsystem Bus (VSB). The DC-1 uses the VSB as an I/O path for data transfers with dual-port memory, array processors and other VSB slave devices. Since the DC-1 is an intelligent controller, the local microprocessor performs complex transfer sequences independently of the VME. A sophisticated mailbox FIFO is used for communication between the DC-1 and other VME devices. The DC-1 supports multiple bus masters on the VSB and block transfer sizes up to 4 Gigabytes in length. The DC-1 is adapted to peripherals with a plug-on I/O module which has a high speed path to a data FIFO on the main board and a control bus for communication with the local processor. Standard I/O modules are available or custom modules can be developed by the customer or Access Dynamics. The data FIFO allows high burst rates and isolates the timing of the VSB from the timing requirements of the peripheral device. Multiple DC-1 based VSB subsystems can be used in the same VME chassis to produce very high performance I/O architectures.

is an I/O Module for the DC-1 VSB I/O Controller. The heart of the DM-17 is an Altera EPM9480-15 complex programmable logic device (CPLD) which is connected to the DC-1 processor and Access Dynamics DM-17 TTL/FPDP I/O Module FIFO data buffer interfaces and to TTL transceivers on the I/O connector. The exact functionality is set by the programming of the CPLD. Clock resources on the DM-17 include a socketed crystal oscillator, the DC-1 processor clock and the VMEbus SYSCLK (16MHz). The DM-17 can be configured to be compatible with the Front Panel Data Port standard (VIAT 17-199X) for both input and output data transfers. An auxiliary connector is provided for general purpose control and external triggering. The CPLD is an Altera EPM9480-15 device and is programmed on the DM-17 through a special JTAG test and programming connector. Once the CPLD is programmed the device retains its logic pattern when power is removed from the board.