IC-FEP-VPX6a Interface Concept Virtex-6 and QorIQ 6U VPX Processing Board

The Interface Concept IC-FEP-VPX6a Virtex-6 and QorIQ 6U VPX Processing Board is controlled by a P2020 processor integrating an e500 v2 Power Architecture core, a DPFPU, an integrated Sec security engine and peripherals, as well as being fully software compatible with the existing PowerPC processors.

The QorIQ provides the usual external interfaces (3*Ethernet, 2*Serial and 3*USB ports). Moreover, one eUSB slot allows to plug an optional SSD module.

The PCIe advanced switch allows versatile coupling between the processor, fabric links of the VPX backplane and the FPGAs. (Non transparent configuration possible for VPC fabric link).

Other Fabric Links of the VPX backplane are directly connected to the FPGAs GTX transveivers. Moreover, the two FPGAs are directly interconnected via GTX ports - allowing data rate up to 6.5 Gbps, LVDS and single-ended signals.

Each Virtex-6 FPGAs of the IC-FEP-VPX6a is associated with two DDR3 memory banks, supporting a 800 MT/s transfer data rate (per bank), and a bank of SRAM DDRII running at 600 MT/s.

Each Virtex-6 FPGA is interfaced with its own SPI flash (user parameters storage) and through a Spartan-6 to the Mirror flash (local bitstreams storage - up to four bitstreams). Thanks to its PCIe link, this Spartan-6 FPGA (control node) can also manage the downloading "on the fly" of the Virtex-6 bitstreams, offering thus a dynamic reconfiguration of the FPGAs. This control node FPGA is also connected to the backplane via two GTP links.

The FMC sites of the IC-FEP-VPX6a are fully compliant with the FPGA Mezzanine Card standard (VITA 57.1), allowing to install FMC modules provided by IC, third-party or developed by the customers. Each FMC can be equipped with an optional IOs connector to route sixteen differential pairs (100 Ohms) from the FMC module directly to the VPX backplane.