Chameleon Catalina Research VME Module

The DRS Technologies / Catalina Research Chameleon VME Module consists of four Xilinx Virtex-E 1000 FPGAs, providing over four million reconfigurable system gates the user can apply to the application. Connected to FPGAs A, B, and C are independent synchronous SRAM blocks. Each bank is independent and can be used to provide large circular buffers. The FPGAs on the Chameleon VME link together in a ring with dedicated paths: A to B, B to C, and A to C. All three FPGAs also link back to D. These FPGA busses can be clocked at rates up to 133MHz.

The Chameleon VME has three high-speed I/O daughtercard sites compatible with the industry's PCI Mezzanine Card (PMC) standard. By enhancing PMC, the effort to tailor the Chameleon VME to specific I/O requirements reduce to driver integration instead of a full custom I/O daughtercard development task.

On the Chameleon VME board, FPGAs A, B, and C each have a dedicated connection to an I/O daughtercard. For PMC-based I/O applications, these links are separate 64-bit 66 MHz PCI busses. CRI provides a 'ready-to-go' PCI core. The daughtercard tied to FPGA C also contains additional connectivity to the VME64x P2 user defined pins, allowing connections to back plane interfaces such as RACE or Dual RACE++. The Chameleon VME also supports an I/O approach where the user may elect not to use PMC as the interface protocol. For that case, the user's custom daughtercards would be PMC mechanical form factor, but the user would define the interface between the daughtercard and its respective processing element.

The VME bridge is automatically configured from an on-board EPROM at power-up. It has a full VME interface, where the control signals are decoded and translated to a local bus that is provided to the rest of the Chameleon VME resources. Through the VME, the user can read from or write to any of the FPGAs, memories, and daughtercards at standard VME bus rates. The VME is primarily used for configuration, control, and diagnostics.