VTR10012 Joerger Enterprises Eight Channel, 100 MHz, 12 Bit VME Analog Digitizer with Oscilloscope Characteristics

The Joerger Enterprises VTR10012 Eight Channel, 100 MHz, 12 Bit VME Analog Digitizer with Oscilloscope Characteristics is available with 1, 2, 4 or 8 individual 100Mhz analog digitizers with a resolution of 12 bits plus signal averaging for improved SNR in a 6U, VME module. In addition to waveform recording the input has the same features as an oscilloscope, 10M Ω input impedance, full scale offset and single ended or differential inputs. This provides the ability to record a single shot event with high speed and resolution and read it out quickly. This simplifies system analysis and trouble shooting. High resolution and accuracy have been attained with the use of ADC's designed to run at 100Mhz with12 bit resolution. To further improve performance the input signals can be averaged to improve signal to noise response. From 2 to 128 input samples can be selected for averaging and the results stored in memory. Each channel is completely self contained and can store up to 256k samples per channel in SRAM, 2M total in a single width module. The latest ADC's, amplifiers, memory and the use of high speed programmable logic devices make all these features possible. While many high speed modules require a great deal of power, the VTR10012 uses only 13 watts while running at 100Mhz. This is often an important consideration when many of these may be used in a single crate. The ADC uses a pipeline converter with the delay handled internally and is invisible to the user.

To insure high performance each channel contains a wide bandwidth amplifier section. To provide good ADC performance it is driven with a buffered amplifier with a differential input and a differential output which is internally offset to provide an input designed especially for these latest type converters. This isolates the ADC and provides a 10M Ω input impedance with either a single ended or a true differential input. The high input impedance affords the ability to monitor an input signal without loading it down. This type input coupled with its large memory provides the ability to monitor a wave shape over a long period of time. Even when trouble shooting a slow speed system it provides a high speed, high-resolution picture. A difficult feature to accomplish with an analog oscilloscope. When required a lower input impedance can be selected with an on board jumper.

To provide a versatile input range full scale offset is provided using a front panel potentiometer. This allows either bipolar or unipolar input ranges. A test point is included to monitor the offset. The offset can be readout on the VME bus. To make the module even more useful data may be read out while active or idle without disrupting the operation. This allows the data from the ADC to be monitored while active. It provides the ability to operate the module as an ADC or to check each channel's offset and gain. The input is digitized using an internal crystal oscillator or an external clock and loads the data into its internal SRAM. To insure high-speed readout, data can be read out 4 samples at a time from 2 channels using BLT64 onto 64 lines. To increase overall data readout speed a "SPARSE" scan mode is provided. Each channel has a 12 bit register that can be set with a minimum input level. Its output is compared to the converted input level and if it is not exceeded the data is considered invalid. This valid data word can be read out indicating which channels should be read. All channels use a common clock, address, control signals and operate simultaneously. Special care has been extended to insure accurate timing.

The analog inputs have been designed to handle a wide variety of signals. Each channel's analog power and analog ground are individually filtered. This special care in the layout and filtering provide both low channel cross talk and low noise, often a problem with multi-channel analog input modules. When an application requires filtering, external filters are recommended.

Control and status registers are accessed via short addressing. The control registers select the operating parameters for the module. The gate duration register contains the number of samples to be taken after a trigger.

To facilitate data readout two additional memories are provided. One records the memory address at the end of each cycle. The second memory records the time each trigger was received and is taken from the 32 bit real time counter. A trigger counter is provided to record the number of complete triggers received. This information allows the user the ability to know how many triggers were received, their memory addresses and the time the triggers occurred. An event register is also provided that selects the number of triggers to accept and disarm the cycle.

The Model VTR10012 can operate in post trigger, multiple post trigger, pre/post and multiple pre/post trigger modes. The post trigger mode starts digitizing on receipt of a trigger, takes the number of samples set by the gate duration register then stops and sets an interrupt. If Auto Reset is on, the next trigger will reset the location counter to zero and overwrite the previous samples. For multiple post trigger operation, Auto Reset is turned off and each following trigger will not reset the location counter and the samples will be stored sequentially until the memory is full. To account for the timing in multiple trigger operations a 32 bit "real time" counter is provided. The time each trigger is received is stored in memory. This can be readout along with the number of triggers received. If the "Memory Wrap" is off and the cycle is complete, an interrupt is set and further triggers are ignored. If the Wrap mode is on, when the memory fills it will start overwriting data and accept triggers until the module is disarmed.

In the pre/post trigger mode the module starts taking data when the unit is armed and cycles through the memory overwriting old data. Upon receipt of a trigger the module takes the number of samples set by the gate duration register, stops and sets an interrupt. The complete memory is used with the post trigger samples preset by the gate duration. The balance of the memory contains pre-trigger information. For multiple pre/post trigger operation the memory is divided programmably into sections of up to 16. Now each section operates as a pre/post trigger cycle with its address and time stored. At the completion of operation an interrupt is set. This then provides the user a complete picture of the data recorded. The memory addresses, the time the triggers were received and the number of triggers are available. All recording cycles are triggered, either internally or externally. As an added feature this trigger can be delayed digitally by programmable setting of a counter and its clock speed. This could prove useful in operations where there is a time gap when the trigger appears and active recording should begin. In pre/post modes a register is provided to require to set a number of samples to be stored after arm before a trigger is recognized.

To control multiple module operation global commands are available that can be used for commands like arm/disarm, and to enable/disable triggers. This allows the user the ability to control a group of modules and have them work together.