GLD-VME/R Systran MIL-STD-1553 Interface Module

The Curtiss-Wright / Systran / Digital Technology GLD-VME/R MIL-STD-1553 Interface Module uses the latest gate array technology to eliminate most of the components on a typical TTL-based MIL-STD-1553 board. This architecture also significantly reduces power consumption. The host interface is software programmable, eliminating jumpers and switches for memory address, interrupt level and interrupt vector. The MIL-STD-1553 connection is also programmable for type of coupling, termination and connect/disconnect for self test purposes.

You can analyze bus traffic by using the Chronological Bus Monitor to set up filters that sort data transfers down to the subaddress level, and monitor mode commands down to the individual mode codes.

Interrupt packets capture a detailed description of each interrupt. Each 12-word packet gives you a thorough explanation of each interrupt by identifying the operational mode that generated the interrupt. It also gives you interrupt type, data buffer address, transmit and receive command and status words, error information, monitor snapshot and link word information.

Meet minimum intermessage gap time requirements with the multiple data buffer design. The data buffers are designed with handshaking logic to insure data integrity during independent BIU and host data transfers.

The BC mode has its own timer that can be used in conjunction with commands in the Interface Library for bus list timing. The Bus Monitor mode has a separate elapsed timer to time stamp all messages with 32-bit time tags. This timer uses either an external RS-422 signal or the internal 1 MHz clock.

The memory-mapped Curtiss-Wright / Systran / Digital Technology GLD-VME/R MIL-STD-1553 Interface Module, with its software programmable host and MIL-STD-1553 bus interfaces, is easy to install and configure to your system requirements.