XMC-FPGA05F Curtiss-Wright PMC/XMC Module with Quad Fiber-Optics

The Curtiss-Wright XMC-FPGA05F PMC/XMC Module with Quad Fiber-Optics combines data processing and I/O in a single module. The FPGA is closely coupled to all interfaces to minimize data bottlenecks.

The Curtiss-Wright XMC-FPGA05F can be used for a wide range of tasks including remote sensor I/O, data recording and linking systems in real-time. The FPGA can be used to implement custom protocols, data encryption or a network processor.

The Curtiss-Wright XMC-FPGA05F is designed to be a user programmable FPGA resource and is fitted with a Xilinx Virtex-5 SX95T FPGA which is optimized for a high ratio of DSP blocks to standard logic blocks to support high performance signal processing.

The FPGA configuration can be updated and controlled by the host across the PCI/PCI-X or PCI Express (PCIe) interfaces using the FLASH memory to store images. The host issues commands over the PCI/PCIe interface to cause FPGA reconfiguration from any of the stored images. A 'FLASH bypass' mode can be invoked which uses temporary storage in SRAM, instead of FLASH, to provide the FPGA configuration. A bit stream stored in SRAM benefits from faster downloads while bypassing non-volatile storage - useful for secure applications.

Up to four full duplex 'low-rider' Stratos Optical Technologies fiber-optic transceivers can be fitted to the Curtiss-Wright XMC-FPGA05F for front panel connections. The transceivers can be supplied in frequencies ranging from 1.0625 to over 3GB/s with single and multi-mode options. Each transceiver is driven directly by an FPGA RocketIO highspeed serial (HSS) link and gives the developer full control over the fiber-optic data protocol. The flexibility of the Curtiss-Wright XMC-FPGA05F even allows different protocols on different channels, such as Serial FPDP (sFPDP) and Aurora, to be used at the same time (note there are some restrictions on concurrently using several different transceiver frequencies).

The Curtiss-Wright XMC-FPGA05F has a choice of on-board clock sources and, together with flexible multipliers within the Virtex-5 FPGA, allows most major signaling frequencies to be achieved in the standard product.

The Curtiss-Wright XMC-FPGA05F features four banks of DDR2 SDRAM connected to and controlled by the FPGA. The memory banks are available to the developer to use for any purpose. Each memory bank can, for example, be associated with each of the four fiber-optic data streams as large independent data buffers dedicated to each channel, used for look-up tables or DSP processing. Each of the SDRAM banks has a capacity of 128MB and provides a 16-bit data path.

The Curtiss-Wright XMC-FPGA05F includes a PCI/PCI-X interface, supporting up to 133MHz operation, and a PCIe interface. Depending on the interface being used, the board provides at least four DMA controllers.

The PCIe interface uses the Virtex-5 FPGA's RocketIO HSS transceivers and an embedded end-point controller, which is a hard IP block within the Virtex-5 FPGA. The built-in PCIe end-point block supports x4 or x8 lane communications, but can be bypassed to support other protocols like Aurora, sFPDP or Serial RapidIO (SRIO). Protocols like Aurora provide low latency communications at high-speed and can be used as either x1, x4 or x8 wide data paths.

Although the Curtiss-Wright XMC-FPGA05F is intended for high-speed serial I/O and FPGA processing applications, it is also equipped with 64-bit digital I/O that can be used as highspeed differential or single-ended I/O including LVDS. The 64-bit digital I/O is provided through either the board's PMC P14 or XMC P16 connectors connected directly to the FPGA. The choice of P14 or P16 connector I/O is defined through a build option.