Pulsar Leonardo DRS RACEway FFT Compute Element Daughter Card

The DRS Technologies / Catalina Research Pulsar RACEway FFT Compute Element Daughter Card is based upon Mercury Computer's Type-B form factor. It plugs directly onto Mercury's H-style motherboards and integrates seamlessly into the RACEway compute fabric.

PULSAR is based upon CRI’s Pathfinder FFT ASIC and Sojourner address generator (AG) ASIC. The two devices together provide substantial acceleration for frequency domain based algorithms.

The Sojourner AG provides full support for radix instructions, real FFTs, 2D FFTs, stacked transforms, vector/complex multiplies, vector/ complex adds. All address patterns have offset/stride parameters which allow truly flexible and efficient algorithm implementation.

High speed SRAM banks hang off the various ports of the DSP. Processing is achieved by passing data back and forth between 'A' (input) memories and the 'B' (processing) memory while flowing the data through the processor. The 'A', 'B', and 'Q' memory banks are each 128K x 64 bits. The window/reference memory ('C') provides storage for windows, filters, twiddle factors, and/or temporary data storage. The 'C' bank is 256K x 64 bits, and is based upon Pentium cache RAM technology.

Separate RACEway interface chip sets provide dedicated RACEway paths into and out from PULSAR. Combined with separate input, output, and processing SRAM banks, PULSAR fully supports concurrent I/O and processing. This maximizes the daughter card's performance from both an I/O and processing standpoint.