SR5060 Interface Technology LVDS I/O Module for SR5000

The SR5060 LVDS I/O Module provides 32 stimulus pins, 32 tristate output pins, and 32 response pins, operating at 50 MHz, in a single C-size slot. Up to 20 I/O modules may be controlled by the SR5010A Timing/Control Module for a total of 640 I/O pins. Input and output pins are grouped on separate connectors, providing the most efficient method of interfacing to the UUT. Bidirectional capability is accomplished by externally connecting the input pins to the output pins.

The SR5060 I/O Module contains seven separate memory banks, each 64K vectors in depth, for generating stimulus patterns, expected response patterns, and recording UUT response data. The Stimulus Memories consist of the Output, Tristate and Algorithmic Output memories. The Output Memory contains the actual data patterns to be generated to the UUT. Tristate Memory provides tristate control which supports bidirectional I/O. The Algorithmic Output Memory determines which algorithmic pattern will be output. The Response Memories consist of the Expect, Mask, and Algorithmic Expect memories. The Expect Memory contains the expected response data for the UUT and is the basis for input compare operations. The Mask Memory determines which patterns are to be ignored for input response comparison. Algorithmic Expect Memory determines which algorithmic expect pattern will be compared against the UUT input response. Record Memory is used to store either the UUT response data or the result of the comparison between the UUT response data and the expected response pattern.

Each I/O module contains 12 separate timing generators, eight for stimulus edge placement and four for response edge placement. The output pins use four of the stimulus timing generators to define the leading (assert) and trailing (deny) edges of the stimulus signal. Used with data formatting, the output pins acquire the ability to produce clocks and strobes within one test cycle. The response pins use the four response timing generators to define the sample and compare edges to determine when to compare and record UUT response data.

The stimulus pins may be independently programmed for any of the following formats: Non-Return-to-Zero (NRZ), Return-to-Zero (RZ), Return-to-One (RONE), Return-to-Complement (RC), and Return-to-Inhibit (RI). The formats are applied to the selected stimulus pins to force the outputs to the defined state when the pin is not actively driving the programmed state. This allows clocks and strobes of either polarity to be generated in a single test cycle, or allows bi-directional control of data busses.