CVME-965 Cyclone Microsystems Single Board Computer w/ SQ09 10/100 BaseTX Ethernet and SQ10 SCSI-2 (Fast) Modules

The Cyclone Microsystems CVME-965 Single Board Computer features a unique memory architecture designed to address the bottleneck problems of a high speed embedded I/O system. The problem of starve-out arises in high speed systems as the processor and DMA controllers compete for the same memory resources.

Processor starve-out has classically been remedied by utilizing an internal and/or large external cache for the processor to operate out of while DMA Controllers are using the main memory. Unfortunately, caches do not properly address the starve-out issue for an embedded I/O processor. In the embedded situation, the processor's main function is to service interrupts from the I/O devices, inspect new packets and initialize new I/O operations. Caches fall down at these jobs because interrupt service routines and interrupt stack data are quickly bumped out of the cache before they are used again. The headers and data from new packets deposited in memory for the processor by the DMA Controllers, by definition, are never found in the cache and require complex cache integrity circuitry or the cache has to be flushed before this data is accessed.

The i960HD microprocessor performs context switching and interrupt servicing with very low latency. The i960HD processor uses features such as register stack, scratch pad memory, and instruction cache to increase performance and reduce the processor's need for the shared memory. However, the best performance solution is to incorporate a private memory for the processor and a global or packet memory for the I/O devices and the processor to share. The private memory is used to store code, especially interrupt service routines, stacks and variables. Because the processor never has to wait to access the private memory, the performance is analogous to having everything in a large cache, without the cache integrity issues. The shared or packet memory is used for I/O buffers and for I/O packet storage. With universal access to this memory, the data need not be moved to transfer the control of a buffer from the input device to the processor and then to an output device.

The private memory on the CVME965 is configured of hyper page mode (EDO) DRAM, allowing burst accesses such as instruction fetches and stack operations to access data on every clock cycle. Accesses to the private memory can proceed at a sustained rate of 66 Mbytes/second.

The shared packet memory was designed with more flexibility. Located on a field upgradable module, the shared memory may contain from 4 to 32 Mbytes of memory. Burst accesses have been expanded to 32 word bursts using the DRAM's hyper page mode. Arbitration for the shared memory is a hybrid priority/round robin scheme which allows the processor to sneak cycles to the shared memory in between the DMA controller's burst accesses of the memory.