PCI3IP Dynamic Engineering 3-Slot PCI IndustryPack (IP) Carrier

The Dynamic Engineering PCI3IP is a 3 slot PCI IndustryPack carrier module. IndustryPack® Modules are an important part of solutions for Embedded situations. Rugged, small, light .. just right for many applications. IndustryPack Modules require a "carrier" in most cases to adapt them to the system. Dynamic Engineering has carrier solutions for a variety of formats. PCI3IP is designed to support PC computer based solutions.

PCI3IP is part of the IP Compatible family of modular I/O components. PCI3IP provides three IndustryPack module sites in one PCI slot. PCI3IP acts as an adapter, converter, carrier, or bridge between the PCI bus and your IndustryPack hardware. PCI3IP is a half size PCI card compatible with the smallest chassis and the tallest processors that prevent full size solutions.

PCI3IP is supported with Windows compliant [WDM32] drivers for XP and 2000 as well as Linux support. The drivers come with a generic IP driver to allow use with "unknown" IP's <=> IP's that do not have a driver designed yet. For example, third party IP's.

Each slot has a separate clock controller for 8 and 32 MHz operation. The clocks are locked together with a PLL, allowing glitch free operation, and the frequency to be changed on the fly. The state-machine within the bridge design automatically locks to the IP Slot frequency at the start of each access.

A new addition to the design of the PCI3IP is to tag all accesses from the PCI bus. IP Modules can take longer than the PCI response specification leading to the use of retry cycles on the PCI bus. In a single CPU system the retry accesses are done serially. The current IP access will be the correct one to respond to the retry access. In a multi-CPU system it is possible to get out of sequence accesses, and potentially have the IP response sent to the wrong retry access. By storing the PCI parameters for the IP access and only responding to the correct retry cycle; multiprocessor cross contamination is avoided. This feature is new with the revision J PROM. Revision J PROM's can be obtained from Dynamic Engineering should you need to upgrade previously fielded HW for use in multiprocessor systems.

Each slot has resettable fused filtered power. The power is distributed with separated power planes to provide isolation between the slots.

Industry standard 50 pin [ribbon cable] headers are used with the IO connectors. Vertical connectors are provided in all positions. Ribbon cable or discrete wire cables can be interfaced directly with the PCI3IP. Alternatively the HDRterm50 can be used to create a terminal block interface.

Slots A and B are configured to accept two single IP's, or a double wide Industrypack compatible design. Slot C is available for single IP's.

A local reset switch is provided for the IP boards. In addition the IP's can be reset from the control register within the Xilinx via the software interface.

LED's are provided to each of the three IP slots for activity indicators. When each slot is accessed the LED is flashed. The FPGA provides a "one shot" circuit to stretch the "on" time to make it visible. Power indicator LEDs are provided on slot A. An additional six user LEDs are available for debugging or other purposes.

A surface mount "dip switch" is available for configuration control or debugging purposes. The switch values are available to be read via the PCI bus. The switch is used for deterministic control by the driver. When multiple carriers are used in the same system the switch is used to allow the driver and application software to "know" which carrier maps to which handle. Further the slot information for a particular IP is stored to create a "vector" pointing to a specific slot on a specific carrier. Deterministic control of specific interfaces is easily achieved with this system without hardwiring system data into your software. The application software will be more portable and not break when new assets are added to the system (and your PCI addresses change).

IndustryPacks are 16 bit devices and the PCI bus supports 32 bits. The PCI3IP accepts 32 bit PCI accesses and converts them into two 16 bit accesses. The IP accesses can be auto-incremented or static address accesses. With the static access option the upper or lower word can be accessed twice. With auto-incremented addresses both words are read from or written to. One PCI access can be used to write to or read from two IP locations. Our clients have measured a 50% speed improvement from the use of the long word access to the IPs. Byte, Word and Long Word accesses are supported to the IP sites from the PCI bus.

The IP accesses are protected by a watch-dog timer. The timer is started at the beginning of each IP access. If the timer expires before the IP being accessed responds, a bus error internal to the PCI3IP is created. The PCI3IP responds normally to the host, not tying up the PCI bus, and provides status and an optional interrupt to alert the host to the problem with the IP. The Bus Error timer is useful in situations where the software may want to cause a bus error to find out what is installed or where a hung system would have consequences.

Connector positioning is compatible with IP-Debug-Bus will allow the user to isolate and debug the control interface of an IP. The IP-Debug-IO can be used in conjunction with the PCI3IP and IP-Debug-Bus to provide test-points on the IO signals and loop-back capability for the IP.

The PCI3IP has an alternate "mini-map" option available. The standard design provides the full address space to the IP Memory space. The mini-map provides a minimized memory space equal to the ID, IO, and INT spaces with 128 bytes. The total PCI memory space is reduced to 2K with this option.