PCI-NECL-ASN1 Dynamic Engineering Programmable NECL I/O with PCI DMA

The Dynamic Engineering PCI-ECL is a general purpose design with ECL and TTL IO plus a high speed Xilinx Virtex II Pro to control it. NECL, LVPECL and other ECL translators can be installed to meet IO requirements. PCI-ECL features a PLX PCI interface chip with DMA support coupled with a Virtex II Pro device to support your design requirements. Dynamic Engineering can design a solution for you or you can implement one too. The Xilinx is reconfigurable, and supported with reprogrammable FLASH. The reference design contains the interfacing to the PLX with DMA support, FIFO, IO and PLL. The reference design is supported with a Windows® driver which has the capability to support your changes without having to write a new driver. We can of course make a new driver with direct calls to your hardware design implementation. The ECL IO is carefully routed to provide 100 ohm differential impedance, and matched length from the pin edge on the D100 connector to the Xilinx [BGA] Ball. All of the TX are matched and all of the RX are matched to allow for high speed designs with tight timing requirements. One ECL input bit is tied to a clock capable input pin on the Xilinx to allow for an external reference clock. The Xilinx is supported by a programmable PLL. The PLL is programmed with a serial bus via the Xilinx control register set. The Windows® driver handles this function. We recommend using the Cypress calculator to determine the PLL settings. The PLL supplies three clocks to the Xilinx which can be used for custom state-machine support. The clocks are received on dedicated clock pins. In addition to the PLL a customer selected oscillator position is supplied. The oscillator can be used if an exact frequency match is required which can't be synthesized with the PLL using the PCI clock as a reference. The base design uses a PCI doubled rate of 66 MHz as the reference for the PLL.

The ECL section has 20 inputs and 20 outputs. The state-machine can be programmed to use any number of the IO.. The remaining IO can be used for a general purpose parallel port. Serial and Parallel interfaces can be implemented. For example, with a 4 wire serial interface a 16 bit parallel port will be available. The external FIFO is used to store data from reception or for transmission. The FIFO is large enough that the IO can operate without interruption. The system can "go away" for up to 24 mS with a 170 MHz serial data stream and not under or over flow the memory. The Internal FIFO is to support DMA. The data is pipelined into or out of the FIFO under control of the scatter gather DMA engine. Data can also be moved with non DMA read or write operations. Data stored into the FIFO is moved to the external FIFO and vice-versa. A state-machine moves the data with a burst transfer when there is sufficient data to move and single transfers when near the boundary conditions. The state-machine for the data transfer operates autonomously. Multi-board operation is supported. With multiple PCI-ECLs in your system and unique cabling, sensors etc. for each slot it is important to "know" which PCI-ECL is which. A surface mount "dip switch" is provided which provides an identifier to the software. A specific PCI-ECL can be matched up with the PCI address allocated to make for deterministic control. The switch can also be used for other purposes; configuration control or debugging for example. The switch values are available to be read via the PCI bus.

The reprogrammable FLASH memory stores the Xilinx design file. The JTAG header is used to load the FLASH using the Xilinx standard IMPACT® software and parallel download cable. PCI-ECL can be ordered with a standard IO control design or updated with a customer specific design via the FLASH. If you prefer to design your own interface; the -ASN1 version HTML is available as part of the engineering kit. When Dynamic Engineering creates a new design the new design is named PCI-ECLSTANDARD-Customernamedesignnumber. For example the PCI-NECL-XG1 is the first NECL based version done for the XG company. The new design will be fully documented and the manual available from this web page. Dynamic Engineering is available to engineer customer specific solutions using PCI-ECL and other Dynamic Engineering designs. Please contact engineering@dyneng.com or call and ask to speak with one of our knowledgeable technical sales staff to help you with your implementation requirements.