PCI Altera 485 Dynamic Engineering Module with Internal D100 Connector

The Dynamic Engineering PCI Altera 485/LVDS I/O Module comes with everything you need to load your Altera program into the 20K400E. Fantastic for development, simulation, special purpose interfaces, multiple serial and / or parallel channels.

The PCI compatible PCI-Altera-485/LVDS design is for the advanced user who wants to implement their own Altera design or requires reconfigurable logic. The PCI-Altera-485/LVDS makes the implementation and use of the 20K400E easy.

The design comes with the basic features built in and the specific features ready for you. The PLX9054 and Xilinx take care of the PCI interface for initial loading of the Altera, and DMA transfer of data into and out of the FIFOs. The Altera controls 40 programmable RS-485 or LVDS transceivers and 12 TTL IO. Each of the RS-485 or LVDS channels is programmable for direction, termination and function. The 12 TTL IO can be inputs or outputs. Eight Cypress 22393 PLL´s support the Altera providing the ability to synthesize multiple reference rates. The only thing missing is your input in the form of a coprocessor, reconfigurable logic, state-machine, simulated system, asynchronous or synchronous data processing.

The PLX 9054 provides a 33/32 PCI interface with bus master capabilities. The 9054 and Xilinx are used to move data to the Altera for output channels and to move data to the host for input channels. 8 input and 8 output FIFO´s are provided to support 8 bi-directional channels. The intermediate FIFO´s are byte wide. The PCI bus is 32 bit oriented. A 1K x 32 FIFO is used to convert the byte wide data to long word prior to DMA or post DMA depending on the direction of data transfer. The 16 intermediate FIFO´s have programmable flags which can be used to cause interrupts for flow control.

IO is accomplished via RS-485 or LVDS transceivers or TTL buffers. The RS-485 transceivers are rated for 40 MHz. The LVDS is rated for 200 MHz. Each transceiver can be controlled for direction and termination. The TTL IO is implemented with 125 open drain drivers with on-board pull-ups. The input direction is buffered with a receiver to protect the Altera and to provide level shifting between the 5V IO and the 3.3V Altera IO. The D100 [ SCSI II 100 pin connector ] provides an easy to interconnect cabling system. The pinouts are consistent with the industry standard differential pairings. The HDEterm100 supports the D100 with a cable to terminal strip conversion.

An 8 position dip switch is provided. The switch is read through the Xilinx. The switch can be used to distinguish multiple PCI_Altera_485 boards in the same system or for other user determined purposes. In addition a pair of shunts is provided on the Altera which can be used to select modes or for any other user defined purpose.

Six LED´s are provided. One is controlled via the Xilinx and can be used for any user purpose. A second LED is for 3.3V regulator power status and the last 4 are controlled via the Altera and the user design. The LEDs can be used for debugging or for system status etc.

The PCI clock is buffered with a zero delay buffer. The PCI side of the PLX 9054 is connected with the PCI required trace length. The clock signal is buffered with 3805 clock drivers and controlled length terminated clock distribution. The local side of the PLX, Xilinx, both sides of the 1K x 32 FIFO, Altera, the input side of the TX FIFOs, and the output side of the RX FIFO´s are provided the distributed clock. All of the clocks and pulsed control signals are terminated with series at the source and parallel at the destination, and length matched for clean and coherent clock distribution and control. The Altera driven and read sides of the FIFOs are provided clocks and controls from the Altera for maximum user control. The PLL´s can be used to create the local references. The signals are terminated with 22 ohms at the source and 1K pull-up at the FIFO. The FIFOs can provide rate matching between the Altera interface "native" speed and the PCI speed.

The PCI Altera design has been upgraded several times based on customer requests for new features. The LVDS and most recently the PROM addition are examples. With the PROM the user can pre-load the Altera during the power on sequence. The PROM is FLASH based and can be reprogrammed via the supplied JTAG header. A shunt can be used to select between the PROM and the Xilinx as the source of the Altera programming file. Revision F and later have the option to install the PROM. Revision G and later have one additional feature which is to be able to load from the PROM and later load from the Xilinx under software control. With Revision F the shunt selects one or the other. With Revision G the shunt selects the initial load after power up.