IP-BiSerial-NG2 Dynamic Engineering Bi-Directional Serial Data Interface

The Dynamic Engineering IP-BiSerial-NG2 Bi-Directional Serial Data Interface is part of the IP Module family of modular I/O components. The IP-BiSerial is capable of providing multiple serial protocols. The standard protocol implemented provides a data, clock and strobe interface with ready control. The –NG2 version is a custom modification featuring the use of two synchronization signals, 32 bit data with parity programmable delays and edge definitions.

The IP-BiSerial-NG2 supports both 8 and 32 MHz IP Bus operation. The IP Clock and on-board oscillator are used to derive the reference clocks for the serial operation. Please be sure to select the proper clock divisors and source selector after reset to insure proper operation. Both single ended and differential I/O are available on the serial signals. The differential drivers and receivers conform to the RS-485 specification (exceeds RS-422). The RS-485 input signals are terminated with 180 Ω. The single ended driver signal is characterized as an open drain driver with 24 mA of sink. For convenience A 2K Ω pull-up is supplied on board, for faster termination a second pull-up can be added at the receiving end of the circuit. Single ended signals are received through 33 Ω resistors. Care should be taken with the single ended signals, as transients can damage the board. The IP-BISERIAL-NG2 conforms to the VITA standard. This guarantees compatibility with multiple IP Carrier boards. Since the IP maintains plug and software compatibility while mounted on different form factors, system prototyping may be done on one IP Carrier board, with final system implementation done on a different one.

The serial channels are supported by 32K by 16 bit FIFOs, which support word accesses. An on-board read/write path exists for loop-back testing. The serial receive channel looks for data in 32 bit transfers. The received bit stream is loaded into the input FIFO. The data length loaded is determined by the programmed word count. The host can poll or wait for the message complete or FIFO almost-full interrupt. The message can be read directly from the input FIFO. Several error conditions are checked including parity, framing, and over-run.