IP-QuadUART-485-PA2 Dynamic Engineering Backplane RS-485 Bus Emulator IP Module

The Dynamic Engineering IP-QuadUART-485-PA2 Backplane RS-485 Bus Emulator IP Module is part of the IP Module family of modular I/O components. It is based on the IP-QuadUART-485 with the UART and all of the IO removed except for two RS-485 transceivers. Also the Xilinx FPGA has been enhanced to an XC2S100 in order to have enough internal block-RAM to accommodate the design.

The module consists of two independent interfaces that send and receive 16-bit words using RS-485 transceivers. The data is sent msb first at a 4 Mbit rate with one preceding start bit. The marking state of the link is low and the start bit is high.

The target interface is the focus of the module, but a master interface is also implemented to allow for standalone testing of the module.

All transactions are instigated by the master interface and consist of either a read or a write command and a 16-bit data word to be written to a write register or that was read from a read register. The module has 64 read registers at offset 0 - 0x7E in the IP MEM space and 64 write registers at offset 0x80 - 0xFE. These registers can be both written and read from the IP bus, but can only be read or written over the RS-485 bus.

The IP-QuadUART-485-PA2 supports both 8 and 32 MHz IP Bus operation. The ID, IO, MEM, and INT spaces are used by the IP-QuadUART-485-PA2 design.

The IP-QuadUART-485-PA2 conforms to the VITA standard. This guarantees compatibility with multiple IP Carrier boards. Because the IP may be mounted on different form factors, while maintaining plug and software compatibility, system prototyping may be done on one IP Carrier board, with final system implementation on a different one. The PCI3IP card makes a convenient development platform in many cases.

Interrupts are supported by the IP-QuadUART-485-PA2. These consist of data received and framing error interrupts for both the master and target interfaces and an overrun error interrupt for the command FIFO. The interrupt conditions are individually maskable. The interrupt occurs on IntReq0. The vector is user programmable by a read/write register and can be read in the IO space or automatically when the INT space is accessed.